1. Technical Field
Described herein are a semiconductor device, a capacitor, and a field effect transistor.
2. Related Art
Most part of the power consumption in a MISFET (metal insulator semiconductor field effect transistor) is caused by the contact resistance between the metal and the source and drain. This is because a Schottky barrier is formed at the interface between the semiconductor and the metal, and the barrier forms electric resistance. In recent years, the proportion of the contact resistance in the power consumption of MISFETs is rapidly increasing, and there is a demand for a decrease in the contact resistance.
To counter this problem, a thin insulating film is inserted into the interface between a Si substrate and a metal provided on the Si substrate, so as to reduce the interaction between Si and the metal. In this manner, the Schottky barrier is lowered (see JP-A 2006-100387(KOKAI), for example). In such a case, the resistance due to the Schottky barrier is lowered, but carriers tunnel through the thin insulating film. Therefore, the tunnel barrier forms new resistance.
Although the pinning by MIGS (metal induced gap states) is eliminated by the thin insulating film formed at the interface, the new resistance due to the tunnel barrier is added, and there is a limit to realization of lower contact resistance. Since the work function varies among metals, the work function cannot be freely controlled.
Likewise, a thin insulating film is inserted into the interface between a Ge substrate and a metal formed on the Ge substrate, so as to reduce the interaction between Ge and the metal. In this manner, the Schottky barrier is lowered (see “Ext. Abst. International symposium on control of semiconductor interface” by T. Nishimura et al., p.p. 67-68, 2007, for example). With the thin insulating film, the position of the pinning by MIGS (metal induced gap states) is successfully changed. However, the effective work function is adjusted only to 4.2 eV, while the target value is 4.0 eV. Although the resistance due to the Schottky barrier is lowered, carrier electrons also tunnel through the thin insulating film in this case. As a result, the tunnel barrier forms new resistance. Therefore, by the technique disclosed in “Ext. Abst. International symposium on control of semiconductor interface” by T. Nishimura et al., p.p. 67-68, 2007, the position of the pinning can be changed, but the work function cannot be adjusted freely, and an optimum work function is not obtained. Although the Schottky barrier is lowered, the new resistance due to the tunnel barrier is added, and there is a limit to realization of lower contact resistance.
According to either of the techniques disclosed in JP-A 2006-100387(KOKAI) and “Ext. Abst. International symposium on control of semiconductor interface” by T. Nishimura et al., p.p. 67-68, 2007, a stacked structure formed with a semiconductor, a thin insulating film, and a metal is formed. Although the Schottky barrier can be lowered in this case, a high tunnel barrier is formed at the interface. There are roughly two problems in this case.
The first problem is that the connecting effect between the semiconductor and the metal does not completely disappear, and therefore, the pinning position shifts. In this case, the pinning position does not always shift to the position of an optimum work function. For example, as disclosed in JP-A 2006-100387(KOKAI), in a case where an oxide film is inserted to the interface between n-type Ge and a metal, an effective work function of approximately 4.2 eV is obtained. Originally, an ideal effective work function should be 4.0 eV, or even 3.9 eV or smaller. According to this technique, however, the effective work function is fixed at 4.2 eV. This value does not greatly vary even if the thickness of the oxide film to be inserted is changed, or if the metal is changed. Therefore, there are no solutions to this problem.
The second problem is that electrons tunnel through the inserted thin film, and allows a current to flow. A tunnel barrier is formed as new resistance, resulting in an increase in the power consumption. If the thin film is made as thin as possible or is made too thin, the effect to shift the pinning position becomes smaller.
In a semiconductor device such as a low-power-consumption MOSFET of the next generation or later, a novel technique is necessary to optimize the effective work function and minimize generation of new resistance.